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Memory Hierarchy#

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Technology and Optimizations#

Main memory#

  • Latency:
  • acess time: time to read/write a word
  • cycle time: time between successive accesses

  • bandwith: the time to retrieve the rest of the block

  • SRAM(Static random access memory): Don't need to be refreshed, so access time is very close to cycle time

  • DRAM(Dynamic random access memory): DRAMs are commonly sold on small boards called DIMM (dual inline memory modules), typically containing 4 ~ 16 DRAMs

technique

介绍了三种cache技术,具体可以见机组

具体分为了RAS（行地址选择）和CAS（列地址选择）两个部分 20241024225306.png

DRAM improvements#

  • Timing signals
  • Leverage spatial locality
  • Clock signals
  • SDRAM
  • Wider DRAM
  • DDR(double data rate) SDRAM
  • Multiple banks

Cache performance#

\[ \text{Average hit time} = (1 - \text{miss rate}) \times \text{cache access time} + \text{miss rate} \times \text{miss penalty} \\ = \text{cache access time} + \text{miss rate} \times \text{miss penalty} \]

Six basic cache optimizations#

  • Larger block size
  • Bigger cache
  • higher associativity
  • multilevel caches
  • Give priority to read misses
  • Avoiding address translation during indexing of the cache 20241024234144.png

Capacity vs Conflict

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cache寻址

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Virtual Memory#

Background 4 Questions#

  • Where to place a block
  • 20241024234521.png 20241024234540.png
  • Which block to replace upon a virtual memory miss? (LRU)
  • Which block to replace upon a virtual memory miss? (Write back or write through)
\[ \text{Virtual memory} = \text{main memory} + \text{Secondary storage} \]

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Ten advanced cache optimizations#

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  • Small and Simple First-Level Caches
  • Way Prediction
  • Multibanked Caches (Pipelining Access)
  • Nonblocking Caches
  • Critical Word First
  • Merging Write Buffer
  • Compiler Optimization
  • Hardware Prefetching
  • Compiler Prefetching
  • HBM

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Virtual Memory#

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Last update: 2024年10月30日 20:23:45
Created: 2024年10月29日 20:50:57